1. Field of the invention
The invention relates to an electrostatic discharge (hereafter referred to as "ESD") protection circuit for an integrated circuit (IC) and, in particular, to an input/output ESD protection circuit of a Metal-Oxide-Semiconductor (MOS) IC which can protect the internal circuitry of the MOS IC from electrostatic discharge damage.
2. Description of the Related Art
A MOS device in a MOS IC includes a drain, a gate, and a source, all formed within a body. The body of the MOS device may be a substrate or a well region of the substrate where the MOS device is formed. The drain and source are spaced a lateral distance from each other and are formed by two doped regions in the substrate or in the well region of the substrate by using a diffusion or ion implantation method. The gate is located on the substrate between the drain and source to control the on/off states of the channel between the drain and source. Generally, the gate consists of a gate oxide layer and a conduction layer formed by a silicon oxide layer and a polysilicon layer, respectively. The MOS device is used as a "controlled source" and a "controlled switch" and the control signal is inputted to the gate.
The gate oxide layer in the MOS device is formed by an extremely thin silicon oxide layer, approximately several hundred .ANG. in thickness. The dielectric breakdown strength of the silicon oxide is about 12.times.10.sup.6 V/cm, so the maximum breakdown voltage of the gate oxide layer (silicon oxide layer) is several tens of volts. For example, the gate oxide layer of 150 .ANG. in thickness can bear a maximum breakdown voltage of about 18 V. In the normal operation of the MOS device, the input voltage is always less than the maximum breakdown voltage mentioned above. However, a voltage in excess of the maximum breakdown voltage may appear on input pins of the MOS IC due to ESD. There are many sources of electrostatic stress, such as human body contact as well as those occuring during the measurement, installation, and operation of MOS ICs. Electrostatic stress may damage or shorten the life of MOS ICs.
Therefore, an ESD protection circuit is typically disposed between an input/output port of the MOS IC and an internal circuit to protect internal MOS devices from damage. A conventional ESD protection method provides a conduction path to a power source line or a ground (i.e., a high voltage source V.sub.DD and a low voltage source V.sub.SS in the MOS IC) between the input/output port and the internal circuit, so the ESD will directly pass through the conduction path to protect internal MOS devices from damage when electrostatic stress is applied to the IC.
An input/output buffer driver device for the MOS IC is generally used as an input/output ESD protection circuit. Only when the electrostatic stress enters the MOS IC from the input/output port, does the buffer driver device provide a bipolar discharge path to accomplish the ESD protection function. So far, there are two input/output ESD protection circuits. One is an NMOS input/output ESD protection circuit; the other is a CMOS input/output ESD protection circuit. Basically, the NMOS input/output ESD protection circuit is similar to the CMOS input/output ESD protection circuit, so, only the CMOS input/output ESD protection circuit will be explained here.
Referring to FIG. 1, a schematic view shows the conventional CMOS input/output ESD protection circuit. An input/output port 2 is a bonding pad through which the signal received by the right-hand circuit of FIG. 1 can be outputted and through which the outside signal can also be inputted to the left-hand circuit of FIG. 1. However, unlike normal signals, when electrostatic stress is applied to the input/output port, the electrostatic stress will pass through the right-hand and left-hand circuits simultaneously. As shown in FIG. 1, the left-hand circuit consists of a PMOS 6 and an NMOS 8 which are connected to each other in series and coupled between a high-voltage source V.sub.DD and a low-voltage source V.sub.SS. The left-hand circuit serves as the input buffer of the IC. A diffusion resistor 4 is constructed by an N-type diffusion region formed in the P-type semiconductor substrate in order to protect the internal circuitry of the CMOS IC. The N.sup.- -type diffusion region and P-type semiconductor substrate can form a PN junction diode. When electrostatic stress applied to the input/output port is higher than the breakdown voltage of the PN junction diode, an ESD path will be formed to protect the internal circuit from damage. Similarly, the diffusion resistor 4 can also be constructed by a P-type diffusion region formed in an N-type well region. Generally, the N-type well region is used to form a PMOS device and is connected to the high-voltage source V.sub.DD. In summary, the diffusion resistor 4 formed by an N-type diffusion region can limit negative-going transition electrostatic stress while the diffusion resistor 4 formed by a P-type diffusion region can limit positive-going transition electrostatic stress. The right-hand circuit consists of a PMOS 12 and an NMOS 14 connected to each other in series and coupled between the high-voltage source VDD and low-power source V.sub.SS. This right-hand circuit serves as the output buffer of a CMOS IC wherein the PMOS 12 is called a pull-up transistor and the NMOS 14 is called a pull-down transistor. This circuit differs from the left-hand circuit in that the drains of the PMOS 12 and NMOS 14 are connected to the input/output port, and not the gates. So the ESD path can be created by the sources, drains and bodies of the PMOS 12 and NMOS 14.
Moreover, with continuous device miniaturization, the ESD problem gets increasingly worse. First, the ESD effect is related to device size. The smaller the device size, the lower the sustainable ESD stress. That is, the ESD protection circuit must have stronger ESD immunity before real protection can be attained. Second, the lightly-doped drain (LDD) commonly used in a submicron process is not suitable for use in an ESD protection circuit because the device having a LDD structure may create local hotspots resulting in advance device damage as electrostatic stress is applied.
Currently, there are many methods for improving the ESD protection of MOS ICs in a submicron process. The first method is to connect a resistor in series to each of the pull-up and pull-down transistors to create a uniform breakdown effect on the ESD path. However, a device having a larger width is needed. The second method is to connect a MOS device in parallel to the pull-down transistor to increase the effectiveness of the ESD path from the input/output port to the low-voltage source V.sub.SS (a ground). However, although the method can provide efficient protection for positive electrostatic stress, the method is not effective for protecting against negative electrostatic stress.